Article # 613, added by Geoworks, historical record
| first |
previous |
index |
next |
last |
80x86 interrupts
Q. On 80x86, what are some examples of maskable interrupts that are not IRQ's? Can divide-by-zero interrupt or "INT 21h" interrupt happen when the interrupt flag is clear? A. IRQs are the exception rather than the rule. They are only maskable because the CPU has the ability to ignore the INT signal generated by the interrupt controller (by clearing the interrupt flag) and because the interruper controller itself can mask out the interrupt request. Interrupts are not maskable, but some can be prevented at the source. This is what happens when you mask an IRQ (the interrupt controller prevents the INT signal from being raised) or if you CLI (the CPU ignores the INT line). Exceptions, like divide-by-zero, will generate an interrupt no matter what. It does not use the INT signal, it is generated internally by the CPU. Likewise, INT21h is a software interrupt. If some software is running with interrupts disabled and executes an INT 21h (or INT anything, really), then the INT 21h handler will be executed no matter the state of the Interrupt flag. The way an IRQ happens is that the PIC (interrupt controller) has a signal raised on one of its IR (interrupt request) lines. If that IR isn't masked and an interrupt of a higher priority isn't currently being services (EOI hasn't been sent yet), the PIC will raise the INT line to the CPU. When the CPU is ready to process the interrupt (Interrupt flag must be set!), the CPU will respond with an INTA (interrupt acknowledgement) signal which tells the PIC that the next interrupt will be serviced. Then the CPU generates another INTA signal (after INT is lowered?) that tells the PIC to put the offset into the interrupt table on the bus. The CPU reads this offset and generates the appropriate interrupt (INT8 for IRQ0, for example). I thought it was interesting that the actual offset into the interrupt table comes from the PIC, not the CPU, but anyway. Once the interrupt handler has completed, the EOI (end of interrupt) is sent to the PIC. If another, lower or equal priority interrupt has occurred, the cycle repeats. That's probably more than you wanted to know, but I thought I should share this wonderful information that I read from an 8259 Intel PIC spec a couple of years ago. By the way, the NMI is also just another INT (INT 2, to be exact). It is generated by the CPU similarly to how divide-by-zero is generated, although external sources can generate it by raising the CPUs NMI line. Contrary to its name (non-maskable interrupt), it can be masked. There is a bit in some I/O register (I can't remember which one.. PORTB, I think?) that prevents the CPU from generating an NMI. Keep in mind that it's maskable only with external hardware, as opposed to INT. Note also that having the PIC provide the vector number means the PIC can be told to place those IRQ levels anywhere in the interrupt table you want. The PC designers decided to put them at INT8, but got wise when the AT came along and put them at 70, out of the space Intel had reserved for their own use (and which Intel used in the 80286 and later chips).